Florian Deeg is an experienced FPGA developer and a PhD candidate at Friedrich-Alexander University Erlangen-Nuremberg, specializing in the design of asynchronous circuits in FPGAs. He is currently leading a project focused on the implementation of an asynchronous RISC-V processor using low-level primitives in Verilog HDL. Florian has a strong background in programming languages and embedded system development. He has published several papers on asynchronous design and safety-critical systems, which have been featured at international conferences. He holds a Master's degree in Electrical Engineering and Information Technology from Friedrich-Alexander University Erlangen-Nuremberg and a Bachelor's degree in Industrial Engineering with a focus on Electrical Engineering from HTWG Konstanz.
FPGA developer,
This work presents a connection between asynchronous circuits and artificial intelligence (AI), with a particular focus on the implementation and optimization of asynchronous designs in field-programmable gate array (FPGA) architectures. It is demonstrated how low-level asynchronous circuits can be designed with the specific intention of being used with FPGAs. This allows the inherent advantages of asynchronous systems, such as reduced latency and energy efficiency, to be utilized for AI workloads. FPGAs are employed in this context as accelerating hardware platforms, which represent a promising solution for AI applications due to their flexibility and performance. The results illustrate the potential of asynchronous FPGA designs as efficient accelerators for AI and open up new avenues for the development of energy-efficient, high-performance hardware solutions in artificial intelligence.